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1. Field of the Invention
The present invention relates to data communications networks and, more particularly, to switching data frames through data communications networks.
2. Description of the Related Art
Frame processing is performed at nodes of networks, such as local area networks (LANs). By processing frames, the nodes are able to determine how to forward or switch frames to other nodes in the network.
FIG. 1 is a block diagram of a conventional frame processing apparatus 100. The conventional frame processing apparatus 100 is suitable for use in a LAN, namely a token-ring network. The conventional frame processing apparatus 100 receives data frames from a plurality of ports associated with the LAN. The data frames are processed by the conventional frame processing apparatus 100 to effectuate a switching operation. In particular, data frames received from each of the ports are processed such that they are either dropped or forwarded to other ports being serviced by the conventional frame processing apparatus 100.
The conventional frame processing apparatus 100 includes physical layer interfaces 102, 104, 106 and 108. The physical layer interfaces 102-108 individually couple to a respective port of the token-ring network. Coupled to each of the physical layer interfaces 102-108 is a token-ring chip set. In particular, token-ring chips sets 110, 112, 114 and 116 respectively couple to the physical layer interfaces 102, 104, 106 and 108. As an example, each of the token-ring chip sets 110-116 includes a TMS380C26 LAN communications processor token-ring chip as well as TMS380FPA PacketBlaster network accelerator and TMS44400 DRAM, all of which are available from Texas Instruments, Inc. of Dallas, Tex.
Although the token-ring chip sets 110-116 could each couple to a data bus directly, to improve performance the conventional frame processing apparatus 100 may include bus interface circuits 118 and 120. The bus interface circuits 118 and 120 couple the token-ring chip sets 110-116 to a data bus 122. The bus interface circuits 118-120 transmit a burst of data over the data bus 122 for storage in a frame buffer 124. By transmitting the data in bursts, the bandwidth of the data bus 122 is able to be better utilized. A frame buffer controller 126 controls the storage and retrieval of data to and from the frame buffer 124 by way of the bus interface circuits 118 and 120 using control lines 128, 130 and 132. The frame buffer 124 stores one or more data frames that are being processed by the conventional frame processing apparatus 100.
An isolation device 134 is used to couple a bus 136 for a microprocessor 138 to the data bus 122. The microprocessor 138 is also coupled to a microprocessor memory 140 and a frame buffer controller 126. The microprocessor 138 is typically a general purpose microprocessor programmed to perform frame processing using the general instruction set for the microprocessor 138. In this regard, the microprocessor 138 interacts with data frames stored in the frame buffer 124 to perform filtering to determine whether to drop data frames or provide a switching destination for the data frames. In addition to being responsible for frame filtering, the microprocessor 138 is also responsible for low level buffer management, control and setup of hardware and network address management.
Conventionally, as noted above, the microprocessors used to perform the frame processing are primarily general purpose microprocessors. Recently, a few specialized microprocessors have been built to be better suited to frame processing tasks than are general purpose microprocessors. An example of such a microprocessor is the CXP microprocessor produced by Bay Networks, Inc. In any event, these specialized microprocessors are separate integrated circuit chips that process frames already stored into a frame buffer.
One problem with conventional frame processing apparatuses, such as the conventional frame processing apparatus 100 illustrated in FIG. 1, is that the general purpose microprocessor is not able to process data frames at high speed. As a result, the number of ports that the conventional frame processing apparatus can support is limited by the speed at which the general purpose microprocessor can perform the filtering operations. The use of specialized microprocessors is an improvement but places additional burdens on the bandwidth requirements of the data paths. Another problem with the conventional frame processing apparatus is that the data path to and from the physical layer and the frame buffer during reception and transmission of data has various bottlenecks that render the conventional hardware design inefficient. Yet another disadvantage of the conventional frame processing apparatus is that it requires a large number of integrated circuit chips. For example, with respect to FIG. 1, the bus interface circuits 118 and 120 are individually provided as application specific integrated circuits (ASICs) for each pair of ports, the token-ring chip sets 110-116 include one or more integrated circuit chips for each port, and various other chips.
Thus, there is a need for improved designs for frame processing apparatuses so that frame processing for a local area network can be rapidly performed with fewer integrated circuit chips.
Broadly speaking, the invention is an improved frame processing apparatus for a network that supports high speed frame processing. The frame processing apparatus uses a combination of fixed hardware and programmable hardware to implement network processing, including frame processing and media access control (MAC) processing. Although generally applicable to frame processing for networks, the improved frame processing apparatus is particular suited for token-ring networks and ethernet networks.
The invention can be implemented in numerous ways, including as an apparatus, an integrated circuit and network equipment. Several embodiments of the invention are discussed below.
As an apparatus for filtering data frames of a data communications network, an embodiment of the invention includes at least: a plurality of protocol handlers of the data communications network, each of the protocol handlers being associated with a port of the data communications network; and a pipelined processor to filter the data frames received by the protocol handlers as the data frames are being received. In one embodiment, the pipelined processor provides a uniform latency by sequencing through the protocol handlers with each clock cycle. Preferably, the apparatus is formed on a single integrated circuit chip.
As an integrated circuit, an embodiment of the invention includes at least a plurality of protocol handlers, each of the protocol handlers corresponding to a different communications port; a receive buffer for temporarily storing data received from the protocol handlers; framing logic, the framing logic controls the reception and transmission of data frames via the protocol handlers; and a filter processor to filter the data frames received by the protocol handlers such that certain of the data frames are dropped and other data frames are provided with a switching destination. Optionally, the integrated circuit further includes a transmit buffer for temporarily storing outgoing data to be supplied to said protocol handlers, and the filter processor further operates to filter the data frames being supplied to said protocol handlers for transmission.
As network equipment that couples to a network for processing data frames transmitted in a the network, an embodiment of the invention includes: a network processing apparatus for processing data frames received and data frames to be transmitted, a frame buffer to store the data frames received that are to be switched to other destinations in the network, and switch circuitry to switch the data frames in said frame buffer to the appropriate one or more protocol handlers. The network processing apparatus includes at least a plurality of protocol handlers, each of said protocol handlers corresponding to a different communications port of the network; and a frame processing apparatus to processes the data frames received from said protocol handlers and the data frames to be transmitted via said protocol handlers.
The advantages of the invention are numerous. One advantage of the invention is that a frame processing apparatus is able to process frames faster, thus allowing the frame processing apparatus to service more ports than conventionally possible. Another advantage of the invention is that the frame processing apparatus according to the invention requires significantly fewer integrated circuit chips per port serviced.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.